LANs, such as Ethernet or Token-Ring networks, are generally interconnected through a hub. A hub is a system comprised of Local Area Network (hereinafter referred to as “LAN”) adapters that communicate through a switch card containing a switch engine.
One type of switch engine is known as a shared memory switch. A shared memory switch is a device wherein packets received by input ports are stored into memory locations, the addresses of which are determined by queues containing packet destination addresses, with packets being transmitted on output ports as destination addresses are dequeued. Although such a switch provides a relatively low cell-lost rate, it presents a bottleneck due to the memory bandwidth that is needed, segregation of memory space, and centralized control of the memory which causes switch performance to degrade as switch size increases. A traditional approach to designing a large shared memory switch has been to first design a feasibly sized shared memory switch module, and to then interconnect a plurality of such modules in order to build a large switch. A design of this type is known to cause degradation in the performance of systems having a shared memory architecture inasmuch as a growth in switch size will result in a memory access controller having a corresponding increase in the extent of centralized control functions and memory operations, thereby significantly reducing access to shared memory. An expandable switch approach to packet switch architecture comprising a plurality of shared memory switches organized in a single stage preceded by a buffer-less interconnection network does not allow global sharing of memory space among all inputs and outputs. It is known that such an approach does not provide optimum memory utilization, as memory belonging to a group of output ports may overflow under unbalanced or bursty traffic conditions.
Another problem of a shared memory switch may arise when the speed of the switch is increased, as input adapters will operate at an increased speed which may be several times the speed used for transferring data packets through the switch engine. In contemporary designs, such a problem is solved by grouping four input ports which are specifically designed to form a link, which is also known as “link paralleling”. A drawback of this particular solution is that a group of two or three, or a number of input ports other than four may not be utilized to form a link. Accordingly, a different sized link adapted to new adapters would require redesign of the link paralleling function of the switch, i.e. a redesign of the switch engine itself.
It is believed, therefore, that a data transmission system which provides the many advantages taught herein would obviate many of the problems and limitations described hereinabove, and would constitute a significant advancement in the art.